PLL-Phase locked Loop

英美

PLL-Phase locked Loop网络翻译

锁相环

章绪论锁相环(PLL-Phase locked loop)是模拟及数模混合电路中的基本模块,是一个能够跟踪输入信号相位和频率,并输出锁定相位,低抖动的系统。

PLL-Phase locked Loop常用短语

1. phase-locked-loop pll：锁相环

PLL-Phase locked Loop双语例句

This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.

介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。

The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).

描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。

Phase-locked loop (PLL) has been applied in many fields.

锁相环在很多领域都得到了广泛应用。

PLL-Phase locked Loop

PLL-Phase locked Loop网络翻译

PLL-Phase locked Loop常用短语

PLL-Phase locked Loop双语例句

相关单词